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Aldec ALINT 2008.10
Aldec ALINT 2008.10 | 90,8 MB
ALINT is an RTL design analysis tool that identifies design issues early in the development cycle. VHDL, Verilog or mixed-language designs are checked for coding inconsistencies, design structure issues, synthesis, simulation, and clock and reset issues prior to synthesis and gate level simulation. ALINT significantly reduces verification time for complex FPGA and ASIC designs, results in uniform, reusable and reliable code and reduces the risk of costly ASIC re-spins. Comprehensive rule sets are available for VHDL, Verilog and mixed-language designs. ALINT includes powerful utilities for rule viewing, editing, violation analysis, and source code cross probing.
* Fast design analysis of complex ASIC/FPGA-SOC designs
* Comprehensive set of rules to check most complex design issues
* Customizable Violation Viewer with Cross-probing to source code
* Advanced framework to set up and configure checks
* User Modified Rules/Rule Sets/Policies
* Supports VHDL, Verilog and mixed-language designs
http://rapidshare.com/files/202696306/aldnogk.rar
يه جايي اين مطلب رو ديدم گفتم شايد شما بدونيد اين چيه ؟
-------------------------------------------------------------------------------------------------------------
Aldec ALINT 2008.10
Aldec ALINT 2008.10 | 90,8 MB
ALINT is an RTL design analysis tool that identifies design issues early in the development cycle. VHDL, Verilog or mixed-language designs are checked for coding inconsistencies, design structure issues, synthesis, simulation, and clock and reset issues prior to synthesis and gate level simulation. ALINT significantly reduces verification time for complex FPGA and ASIC designs, results in uniform, reusable and reliable code and reduces the risk of costly ASIC re-spins. Comprehensive rule sets are available for VHDL, Verilog and mixed-language designs. ALINT includes powerful utilities for rule viewing, editing, violation analysis, and source code cross probing.
* Fast design analysis of complex ASIC/FPGA-SOC designs
* Comprehensive set of rules to check most complex design issues
* Customizable Violation Viewer with Cross-probing to source code
* Advanced framework to set up and configure checks
* User Modified Rules/Rule Sets/Policies
* Supports VHDL, Verilog and mixed-language designs
http://rapidshare.com/files/202696306/aldnogk.rar
